1. Field of the Invention
The present invention relates generally to peripheral circuits of an array of memory cells, and more specifically to a midpoint holding circuit for holding an associated read bus line at a midpoint between discrete logical levels.
2. Description of the Related Art
For each read bus line of a semiconductor memory array, a midpoint holding circuit is provided for holding the associated bus line at a midpoint potential between high and low logical levels. A prior art midpoint holding circuit includes two CMOS inverters and first and second transistor-implemented switches. The first switch is turned on in response to a midpoint control (MC) pulse to supply the bus line potential so that one of the inverters of the flip-flop develops a midpoint potential. When the midpoint control pulse is deasserted, the second switch is turned on instead of the first to cause the inverters to form a flip-flop to hold the associated bus line at the midpoint potential. If high speed read operation is of primary concern, it is necessary to shorten the period of the midpoint control pulse by using CMOS transistors of the type that can carry large currents. However, this results in an increase in heat generation. Additionally, if the sense amplifiers are enabled before the trailing edge of the MC pulse, one of the CMOS inverters has to carry an additional current produced by the corresponding sense amplifier. If the enable timing of the sense amplifiers is delayed with respect to the end timing of the MC pulse, the potential at each bus line is likely to drift to an indeterminate potential. If this potential differs substantially from that subsequently supplied from the corresponding sense amplifier, a substantial amount of delay would result in a read operation. Another problem is the large "cut-through" current that flows in the CMOS inverters when they are simultaneously turned on in response to the associated bus line reaching the midpoint level.